1. Field of the Invention
This invention relates generally to gate or line patterning. More particularly, this invention relates to dark field image reversal for gate or line patterning.
2. Description of the Related Art
Semiconductor critical dimensions (CD) are becoming increasingly smaller to accommodate faster, smaller and more powerful semiconductor devices.
Gate and other line patterning are important aspects for forming semiconductor devices. Typically, bright field masking is used in forming gate and line patterns on a photoresist. Bright field masks are masks where most of the mask is transparent with only a fraction of the mask opaque. However, bright field masking has a problem in that lens aberrations and stray light cause imprecise formation of gate and line patterns, due to the optics utilized in the photolithography process. As a result, CD control in forming gate and line patterns, especially for patterns with critical dimensions less than 100 nanometers, is a problem. Bright field masks are also more prone to particle defect printing. This is especially critical in future lithography systems which may not accommodate pellicle protection of the mask.
Accordingly, it is a general object of the present invention to provide an improved method of forming small contact holes for semiconductor devices.
The above object may be achieved by a method of forming one of a gate pattern and a line pattern for a semiconductor device. The method includes forming a positive resist layer on a substrate. The method also includes irradiating the positive resist layer using a dark field mask, wherein the dark field mask has an opening to allow light to pass therethrough, the opening being equal in size to a dimension of the one of the gate pattern and the line pattern to be formed within the semiconductor device. The method further includes developing the irradiated positive resist layer, so as to remove the irradiated positive resist layer, thereby leaving an opening in the positive resist layer where the irradiated positive resist layer was previously located. The method still further includes applying a negative resist layer to cover the positive resist layer. The method also includes recessing the negative resist so that the negative resist layer exists only within the opening in the positive resist layer. The method further includes exposing the negative resist layer and the positive resist layer to a flood light exposure. The method still further includes applying a developer to the semiconductor device so as to remove the positive resist layer and to harden the negative resist layer. As a result, a resist pattern for forming the one of the gate pattern and the line pattern is formed in a location where the hardened negative resist layer is located.
The above-mentioned object may also be achieved by a method of forming one of a gate pattern and a line pattern for a semiconductor device to be formed on a substrate. The method includes forming a first layer on the substrate, and then forming a positive resist layer on the first layer. The method also includes irradiating the positive resist layer using a dark field mask, wherein the dark field mask has an opening to allow light to pass therethrough, the opening being equal in size to a dimension of the one of the gate pattern and the line pattern to be formed within the semiconductor device. The method further includes subjecting the irradiated positive resist to a developer, so as to remove the irradiated positive resist, thereby leaving an opening in the positive resist layer where the irradiated positive resist layer was previously located. The method still further includes applying a negative resist to cover the first layer and a remaining portion of the positive resist layer. The method also includes recessing the negative resist layer so that the negative resist layer is only disposed within the opening. The method further includes exposing the recessed negative resist layer and the remaining portion of the positive resist layer to a flood light exposure. The method still further includes applying a developer to the semiconductor device so as to dissolve the remaining portion of the positive resist layer and to harden the recessed negative resist layer. As a result, a resist pattern for forming the one of the gate pattern and the line pattern is formed at a location where the hardened negative resist layer is disposed.